The present invention relates to a semiconductor device of a transistor structure having the semiconductor layer compression- or tension-strained, and a method for fabricating the semiconductor device.
Recently, electronic devices, such as transistors, etc., are required to make high-speed operations at low leak currents for high speed and low electric power consumption of information processing and data communication.
As one means for making a transistor speedy, the semiconductor layer to be the channel is compression- or tension-strained by stacking different materials is known. FIGS. 22 and 23 are sectional views of conventional transistor structures which are made speedy by compression- or tension-straining the semiconductor layer to be the channel.
FIG. 22 is a sectional view of a MOS transistor having a Si channel layer which is tension-strained, which shows the structure thereof.
A SiGe buffer layer 202 and a strained Si channel layer 204 are stacked on a p type Si substrate 200. Element isolation grooves 208 which are to be element isolation regions 206 are formed in the SiGe buffer layer 202 and the strained Si channel layer 204. The element isolation grooves 208 define an active region 210 where an element is to be formed.
An element isolation insulation film 212 of a silicon oxide film is buried in the element isolation grooves 208.
Source/drain diffused layers 214a, 214b are formed in the strained Si channel layer 204 and the SiGe buffer layer 202 in the active region 210. A gate electrode 218 is formed on the strained Si channel layer 204 between the source/drain diffused layers 214a. 214b, with the gate insulation film 216 of a silicon oxide film formed between the gate electrode 218 and the strained Si channel layer 204. Source/drain electrodes 220a, 220b are connected to the source/drain diffused layers 214a, 214b. The transistor is thus constituted with the gate electrode 218 and the source/drain diffused layers 214a, 214b formed in the active region 210.
FIG. 23 is a sectional view of a MOS transistor having the SiGe channel layer compression-strained, which shows the structure thereof.
A Si buffer layer 224, a strained SiGe channel layer 226 and a Si cap layer 228 are stacked on a p type Si substrate 222.
Element isolation grooves 232 to be element isolation regions 230 are formed in the Si buffer layer 224, the strained SiGe channel layer 226 and the Si cap layer 228. The element isolation grooves 232 define an active region 234 for an element to be formed in.
An element isolation insulation film 236 of a silicon oxide film is buried in the element isolation grooves 232.
Source/drain diffused layers 238a, 238b are formed in the Si cap layer 228 and the strained SiGe channel layer 226 in the active region 234. A gate electrode 242 is formed on the Si cap layer 228 between the source/drain diffused layers 238a, 238b, with a gate insulation film 240 of a silicon oxide film formed between the gate electrode 242 and the Si cap layer 228. Source/drain electrodes 244a, 244b are connected to the source/drain diffused layers 238a, 238b. The transistor is thus constituted with the gate electrode 242 and the source/drain diffused layers 238a, 238b formed in the active region 234.
It is reported that the above-described structures shown in FIGS. 22 and 23 improve mobility and drive current. However, in the structures shown in FIGS. 22 and 23, in which the element isolation is performed by STI (Shallow Trench Isolation), the element isolation insulation film of a silicon oxide film and the SiGe layer in the active region contact each other at the end of the element isolation regions 206, 230. As a result, as shown in the upper side view of FIG. 24, paths of leak current are formed along the ends of the element isolation regions 206, 230. Accordingly, the transistor has large OFF-state current, which disadvantageously increases electric power consumption of the device.
As a means for suppressing the generation of the leak current due to the contact between the element isolation insulation film of a silicon oxide film buried in the element isolation grooves and the SiGe layer, as exemplified in FIG. 25, the means of forming a layer of polysilicon on the side walls of the element isolation grooves is proposed. That is, sidewalls 246 of polysilicon are formed on the side walls of the element isolation grooves 232, covering the strained SiGe channel layer 226 exposed at the ends of the active region 234. The sidewalls 236 prohibit the contact between the strained SiGe channel layer 226 and the element isolation insulation film 236. However, in forming the sidewalls 236 by this means, the active region 234 is exposed to dry etching.